LOW COMPLEXITY MULTILEVEL 2-D DHWT ARCHITECTURE

Communication

Abstract

In this paper an efficient multilevel 2-D Discrete Haar Wavelet Transform (DHWT) architecture is designed and implemented. The proposed architecture is introduced to compute multilevel 2-D DHWT for image processing applications. The key points of the proposed architecture are its low memory needs and low complexity.
It composes of similar units that can easily compound to decompose the input signal into any required level. The architecture utilizes 4L (L; is the number of decomposition levels) adders and 8M (M is the number of columns of the input image) register stages to perform three levels decomposition with 3+M clock cycles as an initial latency.
The proposed architecture is implemented using Virtex 5 Xilinx FPGA platform. The implementation results reveal that the proposed architecture can operate at up to 110 MHz clock frequency. High output accuracy is also introduced as 63-77 dB PSNR for three-level 2-D DHWT decomposition are obtained.